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3.75 kv, 7-channel, spisolator digital isolators for spi data sheet adum3151 / adum3152 / adum3153 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014C2015 analog devices, inc. all rights reserved. technical support www.analog.com features supports up to 17 mhz spi clock speed 4 high speed, low propagation delay, spi signal isolation channels three 250 kbps data channels 20-lead ssop package with 5.1 mm creepage high temperature operation: 125c high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition per ul 1577 3750 v rms for 1 minute csa component acceptance notice 5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 565 v peak applications industrial programmable logic controllers (plcs) sensor isolation general description the adum3151 / adum3152 / adum3153 1 are 7-channel, spisolator? digital isolators optimized for isolated serial peripheral interfaces (spis). based on the analog devices, inc., i coupler? chip scale transformer technology, the low propagation delay in the clk, mo/si, mi/so, and ss spi bus signals supports spi clock rates of up to 17 mhz. these channels operate with 14 ns propagation delay and 1 ns jitter to optimize timing for spi. the adum3151 / adum3152/ adum3153 isolators also provide three additional independent low data rate isolation channels in three different channel direction combinations. data in the slow channels is sampled and serialized for a 250 kbps data rate with up to 2.5 s of jitter in the low speed channels. functional block diagrams encode control block decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss v ia v ib v oc v dd2 gnd 2 sclk si so sss v oa v ob v ic 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 gnd 1 gnd 2 9 10 12 11 adum3151 12368-001 control block figure 1. adum3151 functional block diagram encode decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss v ia v ob v oc v dd2 gnd 2 sclk si so sss v oa v ib v ic 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 gnd 1 gnd 2 9 10 12 11 adum3152 12368-002 control block control block figure 2. adum3152 functional block diagram encode decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss v oa v ob v oc v dd2 gnd 2 sclk si so sss v ia v ib v ic 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 gnd 1 gnd 2 9 10 12 11 adum3153 12368-003 control block control block figure 3. adum3153 functional block diagram 1 protected by u.s. patents 5,952,849; 6,873,065; 6, 262,600; and 7,075,329. other patents are pending.
adum3151/adum3152/adum3153 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 5 electrical characteristics mixed 5 v/3.3 v operation ........ 7 electrical characteristics mixed 3.3 v/5 v operation ........ 9 package characteristics ............................................................. 10 regulatory information ............................................................. 11 insulation and safety related specifications .......................... 11 din v vde v 0884 - 10 (vde v 0884 - 10): 2006 - 12 insulation characteristics .......................................................... 12 recommended operating conditions .................................... 12 absolute maximum ratings ......................................................... 13 esd caution ................................................................................ 13 pin configurations and function descriptions ......................... 14 typical performance characteristics ........................................... 17 applications information .............................................................. 18 introduction ................................................................................ 18 printed circuit board (pcb) layout ....................................... 19 propagation delay related parameters ................................... 19 dc correctness and magnetic field immunity ..................... 19 power consumption .................................................................. 20 insulation lifetime ..................................................................... 20 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 3 /15 rev. 0 to rev. a changes to features section ............................................................ 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 4 changes to table 5 ............................................................................ 5 changes to table 6 ............................................................................ 6 changes to table 8 ............................................................................ 7 changes to table 9 ............................................................................ 8 changes to table 11 .......................................................................... 9 changes to table 12 ........................................................................ 10 changes to regulatory information section and table 14 ....... 11 changes to table 16 and figure 4 ................................................. 12 changes to figure 8, figure 9, figure 11, and figure 12 ........... 17 changes to high speed channels section .................................. 18 changes to power consumption section .................................... 2 0 6/14 revision 0: initial version rev. a | page 2 of 22
data sheet adum3151/adum3152/adum3153 specifications electrical character istics 5 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 5 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v, and ?40c t a + 125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise note d. table 1 . switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 17 mhz data rate fast (mo, so) dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 25 12 14 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 21 25 21 25 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns v ia , v ib , v ic data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 3 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitc h filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 v ix = v ia , v ib , or v ic . 4 an inter nal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channels is cr itical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. table 2 . supply current device number symbol 1 mhz, a grade 17 mhz, b grade unit test conditions/comments min typ max min typ max adum3151 i dd1 4.0 8.5 14.0 22 ma c l = 0 pf, low speed channels i dd2 6.0 10.5 13.5 23 ma c l = 0 pf, low speed channels adum3152 i dd1 4.8 8 14.0 21.5 ma c l = 0 p f, low speed channels i dd2 6.5 10.5 14.0 22.5 ma c l = 0 pf, low speed channels adum3153 i dd1 4.0 6.5 14.0 21.5 ma c l = 0 pf, low speed channels i dd2 6.0 12 13.3 21 ma c l = 0 pf, low speed channels rev. a | page 3 of 22
adum3151/adum3152/adum3153 data sheet table 3 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions/comments dc specifications mclk, mss , mo, so, v ia , v ib , v ic logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , v oc logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.080 ma/mbps dynamic output supply current i ddo(d) 0.046 ma/mbps supply current for all low speed channels quiescent side 1 current i dd1(q) 4.3 ma quiescent side 2 current i dd2(q) 6.1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , v ib , or v ic pins. 3 i output is the output current of any of the sclk, sss , mi, si, v oa , v ob , or v oc pins. 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 4 of 22
data sheet adum3151/adum3152/adum3153 electrical character istics 3.3 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 3.3 v. minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v, and ?40c t a + 125c , unless otherwise noted. switching specifications are tested with c l =15 pf and cmos signal levels, unless otherwise noted. table 4 . switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 12.5 mhz data rate fast (mo, so) dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 30 20 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 4 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 30 30 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, low speed j ls 2.5 2.5 ns v ia , v ib , v ic data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s |t plh ? t phl | v ix 3 minimum input skew 4 t vix skew 3 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, wher eas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed gra de. 3 v ix = v ia , v ib , or v ic . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channe ls is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. table 5 . supply current device number symbol 1 mhz, a grade/b grade 17 mhz, b grade unit test conditions/comments min typ max min typ max adum3151 i dd1 2.8 6.5 10.5 18 ma c l = 0 pf, low speed channels i dd2 4.6 8 9.0 17 ma c l = 0 pf, low speed channels adum3152 i dd1 3.4 6 11.7 18 ma c l = 0 p f, low speed channels i dd2 5.0 8 10.0 16 ma c l = 0 pf, low speed channels adum3153 i dd1 2.8 5.5 11.7 18 ma c l = 0 pf, low speed channels i dd2 3.5 9 10.0 15 ma c l = 0 pf, low speed channels rev. a | page 5 of 22
adum3151/adum3152/adum3153 data sheet table 6 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions/comments dc specifications mclk, mss , mo, so, v ia , v ib , v ic logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , v oc logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.086 ma/mbps dynamic output supply current i ddo(d) 0.019 ma/mbps supply current for all low speed channels quiescent side 1 current i dd1(q) 2.9 ma quiescent side 2 current i dd2(q) 4.7 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , v ib , or v ic pins. 3 i output is the output current of any of th e sclk, sss , mi, si, v oa , v ob , or v oc pins. 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 6 of 22
data sheet adum3151/adum3152/adum3153 electrical character istics mixed 5 v/3.3 v oper ation all typical specifications are at t a = 25c, v dd1 = 5 v, and v dd2 = 3.3 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v, and ?40c t a + 125c , unless otherwise noted. switching specifications are tested with c l =15 pf and cmos signal levels, unless otherwise noted. table 7 . switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 15.6 mhz 1/(4 t phl ) data rate fast (mo, so) dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 27 16 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 27 26 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns v ia , v ib , v ic data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 3 10 10 ns 1 c odirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier . 2 the mss signal is gl itch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal b y different times depending on speed grade. 3 v ix = v ia , v ib , or v ic . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channe ls is critical to the end application, the leading pulse mu st be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. table 8 . supply current device number symbol 1 mhz, a grade/b grade 17 mhz, b grade unit test conditions/comments min typ max min typ max adum3151 i dd1 4.0 8.5 13.9 22 ma c l = 0 pf, low speed channels i dd2 4.6 8 9.0 17 ma c l = 0 pf, low speed channels adum3152 i dd1 4.8 8 14.0 21.5 ma c l = 0 p f, low speed channels i dd2 5.0 8 10.0 16 ma c l = 0 pf, low speed channels adum3153 i dd1 4.0 6.5 14.0 21.5 ma c l = 0 pf, low speed channels i dd2 4.7 9 10.0 15 ma c l = 0 pf, low speed channels rev. a | page 7 of 22
adum3151/adum3152/adum3153 data sheet table 9 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions/comments dc specifications mclk, mss , mo, so, v ia , v ib , v ic logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , v oc logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for all low speed channels quiescent side 1 current i dd1(q) 4.3 ma quiescent side 2 current i dd2 ( q) 4.7 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , v ib , or v ic pins. 3 i output is the output current of any of the sclk, sss , mi, si, v oa , v ob , v oc pins. 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common - mode v oltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 8 of 22
data sheet adum3151/adum3152/adum3153 electrical character istics mixed 3.3 v/5 v oper ation all typical specifications are at t a = 25c, v dd1 = 3.3 v, and v dd2 = 5 v. minimum and maximum specifications apply ov er the entire recommended operation range: 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v, and ?40c t a + 125c , unless otherwise noted. switching specifications are tested with c l =15 pf and cmos signal levels, unless otherwise noted. table 10 . switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 15.6 mhz data rate fast (mo, so) dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 27 16 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 5 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 2 34 mbps within pwd limit propagation delay t phl , t plh 27 27 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 2 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns v ia , v ib , v ic data rate dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s |t plh ? t phl | v ix 3 minimum input skew 4 t vix skew 3 10 10 ns 1 c odirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inp uts on the same side of the isolation barrier . 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to gua rantee that mss reaches the output ahead of another fast signal, it must be set up prio r to the competing signal by different times depending on speed grade. 3 v ix = v ia , v ib , or v ic . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channels is critic al to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. table 11 . supply current device number symbol 1 mhz, a grade/b grade 17 mhz, b grade unit test conditions/comments min typ max min typ max adum3151 i dd1 2.8 6.5 10.5 18 ma c l = 0 pf, low speed channels i dd2 6.0 10.5 13.0 23 ma c l = 0 pf, low speed channels adum3152 i dd1 3.5 6 11.7 18 ma c l = 0 p f, low speed channels i dd2 6.5 10.5 13.4 22.5 ma c l = 0 pf, low speed channels adum3153 i dd1 2.8 5.5 11.7 18 ma c l = 0 pf, low speed channels i dd2 6.0 12 13.4 21 ma c l = 0 pf, low speed channels rev. a | page 9 of 22
adum3151/adum3152/adum3153 data sheet table 12 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions/comments dc specifications mclk, mss , mo, so, v ia , v ib , v ic logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , v oc logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for all low speed channels quiescent side 1 current i dd1(q) 2.9 ma quiescent side 2 current i dd2 ( q) 6.1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo , so, v ia , v ib , v ic pins. 3 i output is the output current of any of the sclk, sss , mi, si, v oa , v ob , v oc pins. 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. package characterist ics table 13. parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i- o 10 12 ? capacitance (input to output) 1 c i- o 1.0 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to case thermal resistance jc 75 c/w thermocouple located at center of package underside 1 the device is considered a 2 - terminal device: pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. rev. a | page 10 of 22
data sheet adum3151/adum3152/adum3153 rev. a | page 11 of 22 regulatory information the adum3151 / adum3152/ adum3153 are approved by the organizations listed in table 14. see table 19 and the insulation lifetime section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels. table 14. ul csa vde recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 3750 v rms single protection basic insulation per csa 60950-1-07+a1+a2 and iec 60950-1 2 nd ed.+a1+a2, 510 v rms (721 v peak) maximum working voltage 3 reinforced insulation, 565 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each model is proof tested by applying an insulation test voltage 4500 v rms for 1 second (curren t leakage detection limit = 10 a). 2 in accordance with din v vde v 0884-10, each model is proof tested by applying an insulation test voltage 525 v peak for 1 s econd (partial discharge detection limit = 5 pc). the asterisk (*) marked on the comp onent designates din v vde v 0884-10 approval. 3 see table 19 for recommended maximum working vo ltages under various operating conditions. insulation and safety related specifications table 15. parameter symbol value unit test conditions/comments rated dielectric insulation voltage 3750 v rms 1-minute duration minimum external air gap (clearance) l(i01) 5.1 mm min measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 5.1 mm min measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 mm min insulation distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303, part 1 material group ii material group (din vde 0110, 1/89, table 1)
adum3151/adum3152/adum3153 data sheet din v vde v 0884 - 10 (vde v 0884- 10): 2006-12 insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the asterisk (*) marked on packages denotes din v vde v 0884 - 10 approval. table 16. description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 565 v peak input -to - output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 1059 v peak input -to - output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 848 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 678 v peak highest allowable overvoltage v iotm 5000 v peak surge isolation voltage v iosm(test) = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6250 v peak safety limiting values maximum value allowed in the event of a failure (see figure 4) case temperature t s 150 c safety total dissipated power i s1 1.4 w insulation resistance at t s v io = 500 v r s >10 9 ? 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 200 150 100 50 12368-004 safe limiting power (w) ambient temperature (c) figure 4 . thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 recommended operatin g conditions table 17. parameter symbol min max unit operating temperature range t a ?40c +125 c supply voltage range 1 v dd1 , v dd2 3.0 5.5 v input signal rise and fall times 1.0 ms 1 see the dc correctne ss and magnetic field immunity section for information on the i mmunity to the external magnetic fields. rev. a | page 12 of 22
data sheet adum3151/adum3152/adum3153 absolute maximum rat ings t a = 25c, unless otherwise noted. table 18. parameter rating storage temperature (t st ) range ?65c to +150c ambient operating temperature (t a ) range ?40c to +125c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages (v ia , v ib , v ic , mclk, mo, mss ) ?0.5 v to v dd x + 0.5 v output voltages ( sclk, sss , mi, si, v oa , v ob , v oc ) ?0.5 v to v dd x + 0.5 v average current per output pin 1 ?10 ma to +10 ma common - mode transients 2 ?100 kv/s to +100 kv/s 1 see figure 4 for maximum safety rated current values across temperature. 2 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those i ndicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 19 . maximum continuous working voltage 1 paramete r max unit constraint ac 60 hz rms voltage 400 v rms 20- year lifetime at 0.1% failure rate, zero average voltage dc voltage 722 v peak limited by the creepage of the package, pollution degree 2, material group ii 2 , 3 1 see the insulation lifetime section for more details. 2 other pollution degree and material group requirements yield a different limit. 3 some system level standards allow components to use the pri nted wiring board (pwb) creepage values. the supported dc voltage may be higher for those standards. esd caution rev. a | page 13 of 22
adum3151/adum3152/adum3153 data sheet pin configurations a nd function descript ions v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 v i a 7 16 15 14 v ib 8 13 v oc 9 12 gnd 1 v dd2 gnd 2 sclk si so sss v o a v ob v ic gnd 2 10 1 1 12368-005 adum3151 (not to scale) t o p view figure 5 . adum3151 pin configuration table 20. adum3151 pin functio n descriptions pin no. mnemonic direction description 1 v dd1 power input power supply for side 1. a bypass capacitor from v dd1 to gnd 1 to local ground is required. 2, 10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk clock spi clock from the master controller. 4 mo input spi data from the master mo/si line. 5 mi output spi data from the slave to the master mi/so line. 6 mss input slave select from the master. this signal uses an active low logic. the slave select pin requires a 10 ns setup time from the next clock or data edge. 7 v ia input low speed data input a. 8 v ib input low speed data input b. 9 v oc output low speed data output c. 11, 19 gnd2 return ground 2. ground reference for isolator side 2. 12 v ic input low speed data input c. 13 v ob output low speed data output b. 14 v oa output low speed data output a. 15 sss output slave select to the slave. this signal uses an active low logic. 16 so input spi data from the slave to the master mi/so line. 17 si output spi data from the master to the slave mo/si line. 18 sclk output spi clock from the master controller. 20 v dd2 power input power supply for side 2. a bypass capacitor from v dd2 to gnd 2 to local ground is required. rev. a | page 14 of 22
data sheet adum3151/adum3152/adum3153 v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 v ia 7 16 15 14 v ob 8 13 v oc 9 12 gnd 1 v dd2 gnd 2 sclk si so sss v oa v ib v ic gnd 2 10 1 1 12368-006 adum3152 (not to scale) t o p view figure 6 . adum3152 pin configuration table 21. adum3152 pin function descriptions pin no. mnemonic direction description 1 v dd1 power input power supply for side 1. a bypass capacitor from v dd1 to gnd 1 to local ground is required. 2, 10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk clock spi clock from the master controller. 4 mo input spi data from the master mo/si line. 5 mi output spi data from the slave to the master mi/so line. 6 mss input slave select from the master. this signal uses an active low logic. the slave select pin requires a 10 ns setup time from the next clock or data edge. 7 v ia input low speed data input a. 8 v ob output low speed data output b. 9 v oc output low speed data output c. 11, 19 gnd 2 return ground 2. ground reference for isolator side 2. 12 v ic input low speed data input c. 13 v ib input low speed data input b. 14 v oa output low speed data output a. 15 sss output slave select to the slave. this signal uses an active low logic. 16 so input spi data from the slave to the master mi/so line. 17 si output spi data from the master to the slave mo/si line. 18 sclk output spi clock from the master controller. 20 v dd2 power input power supply for side 2. a bypass capacitor from v dd2 to gnd 2 to local ground is required. rev. a | page 15 of 22
adum3151/adum3152/adum3153 data sheet v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 v oa 7 16 15 14 v ob 8 13 v oc 9 12 gnd 1 v dd2 gnd 2 sclk si so sss v ia v ib v ic gnd 2 10 1 1 12368-007 adum3153 (not to scale) t o p view figure 7 . adum3153 pin configuration table 22. adum3153 pin function descriptions pin no. mnemonic direction description 1 v dd1 power input power supply for side 1. a bypass capacitor from v dd1 to gnd 1 to local ground is required. 2, 10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk clock spi clock from the master controller. 4 mo input spi data from the master mosi line 5 mi output spi data from the slave to the master mi/so line. 6 mss input slave select from the master. this signal uses an active low logic. the slave select pin requires a 10 ns setup time from the next clock or data edge. 7 v oa output low speed data output a. 8 v ob output low speed data output b. 9 v oc output low speed data output c. 11, 19 gnd 2 return ground 1. ground reference for isolator side 2. 12 v ic input low speed data input c. 13 v ib input low speed data input b. 14 v ia input low speed data input a. 15 sss output slave select to the slave. this signal uses an active low logic. 16 so input spi data from the slave to the master mi/so line. 17 si output spi data from the master to the slave mo/si line. 18 sclk output spi clock from the master controller. 20 v dd2 power input power supply for side 2. a bypass capacitor from v dd2 to gnd 2 to local ground is required. table 23. adum3151 / adum3152 / adum3153 power - off default state truth table (positive logic) 1 v dd1 state v dd2 state side 1 outputs s ide 2 outputs sss comments unpowered powered z z z outputs on an unpowered side are high impedance within one diode drop of ground powered unpowered z z z outputs on an unpowered side are high impedance within one diode drop of ground 1 z is high impedance. rev. a | page 16 of 22
data sheet adum3151/adum3152/adum3153 typical performance characteristics 0 1 2 3 4 5 7 6 0 20 40 60 80 d at a r a te (mbps) 3 . 3 v 5 .0v 12368-100 dynamic supp l y current per input channe l (ma) figure 8 . typical dynamic supply current per input channel vs. data rate for 5.0 v and 3.3 v operation 0 5 10 15 20 25 30 0 20 40 60 80 i dd1 supp l y current (ma) d at a r a te (mbps) 3 . 3 v 5 .0v 12368-102 figure 9 . typical i dd1 supply current vs. data rate for 5.0 v and 3.3 v operation 0 2 4 6 8 10 12 14 16 ?40 10 60 1 10 pro p ag a tion del a y (ns) ambient temper a ture (c) 3 . 3 v 5 .0v 12368-012 figure 10 . typical propagation delay v s. ambient temperature for high speed channels without glitch filter (see the high speed channels section) 12368-101 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 20 40 60 80 dat a r a te (mbps) 3 . 3 v 5 .0v dynamic supp l y current per output channe l (ma) figure 11 . typical dynamic supply current per output channel vs. data rate for 5.0 v and 3.3 v operatio n 0 5 10 15 20 25 0 20 40 60 80 i dd2 supp l y current (ma) dat a r a te (mbps) 3 . 3 v 5 .0v 12368-103 figure 12 . typical i dd2 supply current vs. data rate for 5.0 v and 3.3 v operation ?40 10 60 1 10 ambient temper a ture (c) 3 . 3 v 5 .0v 0 5 10 15 20 25 pro p ag a tion del a y (ns) 12368-013 figure 13 . typical propagation delay vs. ambient temperature for high speed channels with glitch filter (see th e high speed channels section) rev. a | page 17 of 22
adum3151/adum3152/adum3153 data sheet applications informa tion introduction the adum3151 / adum3152 / adum3153 are a family of devices created to optimize isolation of spi for speed and provide additio nal low speed channels for control and status monitoring functions. the isolators are based on differential signaling i coupler technology for enhanced speed and noise immunity. high speed channels the adum3151 / adum3152 / adum3153 have four high speed channels. the first three channels, clk, mi/so, and mo/si (the slash indicates the connection of the particular input and output channel across the isolator), are optimized for either low propagation delay in the b grade or high noise immunity in the a grade. the difference between the grades is the addition of a glitch filter to these three channels in the a grade version, which increases the propagation delay. the b grade version, with a maximum propagation delay of 14 ns, supports a maximum clock rate of 17 mhz in the standard 4 - wire spi. howev er, because the glitch filter is not present in the b grade version, ensure that spurious glitches of less than 10 ns are not present. glitches of less than 10 ns in the b grade devices can cause the missing of the second edge of the glitch. this pulse co ndition is then seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. it is recommended to use the a grade devices in noisy environments. the relationship between the spi signal paths and the pin mnemo nics of the adum3151 / adum3152 / adum 3153 and the data directions is detailed in table 24. table 24 . pin mnemonics correspondence to the spi signal path names spi signal path master side 1 data direction slave side 2 clk mclk the datapaths are spi mode agnostic. the clk and mosi, spi data paths are optimized for propagation delay and channel to channel matching. the miso spi datapath is optimized for propagation delay. the devices do not synchronize to the clock channels so the re are no constraints on the clock polarity or the timing with respect to the data lines. to allow compatibility with non standard spi interfaces, the mi pin is always active, and does not tri state when the slave select is not asserted. this precludes tying several mi line s together without adding a tri s t ate buffer or multiplexor. the ss (slave select bar) is typically an active low signal. it can have many dif ferent functions in spi and spi - like busses. many of these functions are edge tri ggered, so the ss path contains a glitch filter in both the a grade and the b grade. the glitch filter prevents short pulses from propagating to the output or causing other errors in operation. the mss signal requires a 10 ns setup time in the b grade devices prior to the first active clock edge to allow the added propagation time of the glitch filter. low speed data channels the low speed data channels are provided as economical isolated datapaths where timing is not cri tical. the dc value of all high and low speed inputs on a given side of the devices are sampled simultaneously, packetized and shifted across an isolation coil. the high speed channels are compared for dc accuracy, and the low speed data is transferred to the appropriate low speed outputs. the process is then reversed by reading the inputs on the opposite side of the devices, packetizing them and sending them back for similar processing. the dc correctness data for the high speed channels is handled interna lly, and the low speed data is clocked to the outputs simultaneously. a free running internal clock regulates this bidirectional data shuttling. because data is sampled at discrete times based on this clock, the propagation delay for a low speed channel is between 0.1 s and 2.6 s, depending on where the input data edge changes with respect to the internal sample clock. figure 14 illustrates the behavior of the low speed channels and the relationship between the codirectional channels. ? point a: when data is sampled between the input edges of two low speed data inputs, a very narrow gap between edges is increased to the width of t he output clock. ? point b: data edges that occur on codirectional channels between samples are sampled and simultaneously sent to the outputs, which synchronizes the data edges between the two channels at the outputs. ? point c: data pulses that are less than the minimum low speed pulse width may not be transmitted because they may not be sampled. input a output a sample clock output clock b c input b output b a b c 12368-014 a a figure 14 . slow channel timing a low speed data system that is carefully designed so that staggered data transitions at the inputs become either rev. a | page 18 of 22
data sheet adum3151/adum3152/adum3153 synchronized or pushed apart when they are presented at the output. edge order is always preserved for as long as the edges are separated by at least v ix skew . in other words, if one edge is leading another at the input, the order of the edges i s no t reverse d by the isolator. printed circuit boar d (pcb) layout the adum3151 / adum3152 / adum3153 digital isolators require no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at both input and output supply pins: v dd1 and v dd2 (see figure 15 ). the capacitor value must be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 2 0 mm . by p ass < 2mm 12368-015 v dd1 gnd 1 mclk mo mi mss v ia /v o a v ib /v ob v dd2 gnd 2 sclk si so sss v oa /v ib v ib /v ob v oc gnd 1 v ic gnd 2 adum3151/ adum3152/ adum3153 figure 15 . recommended pcb layout in applications involving high common - mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the board layout so that any coupling th at does occur affects all pins equally on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch - up or permanent damage. propagation delay r elated parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. input output t plh t phl 50% 50% 12368-016 figure 16 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single adum3151 / adum3152 / adum3153 component. dc correctne ss and magnetic fiel d immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than ~1.2 s, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed channel to ensure dc correctness at the output. if the low s peed decoder receives no pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional , in which case, the isolator output is forced to a high - z state by the watchdog timer circuit. the limitation on the magnetic field immunit y of the device is set by the condition in which induced v oltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines such conditions. the adum3151 / adum3152 / adum3153 were examined in a 3 v operating condition bec ause it represents the most susceptible mode of operation for this product. the pulses at the transformer output have an amplitude greater than 1.5 v. the decoder has a sensing threshold of about 1.0 v; th ereby , establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/ dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density. r n is the radius of the n th turn in the receiving coil. n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum3151 / adu m3152/ adum3153 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 17. magnetic field frequency (hz) maximum allowable magnetic flux density (kgauss) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 12368-017 figure 17 . maximum allowable external magnetic flux density rev. a | page 19 of 22
adum3151/adum3152/adum3153 data sheet for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.5 kgauss , induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. if such an event occurs, with the worst - case polarity, during a transmitted pulse, it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum3151 / adum3152 / adum3153 transformers. figure 18 expresses these allowable current magnitudes as a function of frequency for selected distances. the adum3151 / adum3152 / adum3153 are insensitive to external fields. only extremely large, high frequency currents, very close to the component are a concern. for the 1 mhz example noted, a user would have to place a 1.2 ka current 5mm away from the adum3151 / adum3152 / adum3153 to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 12368-018 figure 18 . maximum allowable current for various c urrent to adum3151 / adum3152 / adum3153 spacings at combinations of strong magnetic field and high frequency, any loops formed by the pcb traces may induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. take care to avoid pcb structures that form lo ops. power consumption the supply current at a given channel of the adum3151 / adum3152 / adum3153 isolators is a function of the supply voltage, the data rate of the channel, and the output load of th e channel and whether it is a high or low speed channel. the low speed channels draw a const ant quiescent current caused by the internal ping - pong datapath. the operating frequency is low enough that the capacitive losses caused by the recommended capacitive load are negligible compared to the quiescent current. the explicit calculation for the d ata rate is eliminated for simplicity, and the quiescent current for each side of the isolator due to the low speed channels can be found in tabl e 3 , tabl e 6 , table 9 , and table 12 for the particular operating voltages . these quiescent currents add to the high speed current as is shown in the following equations for the total current for each side of the isolator. dynamic currents are taken from table 3 and table 6 for the respective voltages. f or side 1, the supply current is given by i dd1 = i ddi(d) (f mclk + f m o + f mss ) + f mi ( i ddo(d) + ((0.5 10 ?3 ) c l(mi) v dd1 )) + i dd1(q) for side 2, the supply current is given by i dd2 = i ddi(d) f so + f sclk (i ddo(d) + ((0.5 10 ? 3 ) c l(sclk) v dd2 )) + f si (i ddo(d) + ((0.5 10 ? 3 ) c l(si) v dd2 )) + f sss (i ddo(d) + ((0.5 10 ? 3 ) c l( sss ) v dd2 )) + i dd2(q) where: i ddi(d) , i ddo(d) are the input and output dynamic supply currents per channel (ma/mbps). f x is the logic signal data rate for the specified channel (mbps). c l(x) is the load capacitance of the specified output (pf). v ddx is the supply voltage of the side being evaluated (v). i dd1(q) , i dd2(q) are the specified side 1 and side 2 quiescent supply currents (ma). figure 8 and figure 11 show the supply current per channel as a function of data rate fo r an input and unloaded output. figure 9 and figure 12 show the total i dd1 and i dd2 supply currents as a function of data rate for the adum3151 / adum3152 / adum3153 channel configurations with all high speed channels running at the same speed and the low speed channels at idle. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degrad ation is dependent on the characteristics of the voltage waveform applied across the insulation as well as the materials and material interfaces . there are two types of insulation degradation of primary interest : breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long - term insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allow the components to be categorized in to different material groups. lower material group ratings are more resistant to s urface tracking and, therefore, can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and rev. a | page 20 of 22
data sheet adum3151/adum3152/adum3153 is based on the total rms voltage across the isolation, pollution degree, and material group. the material group and creepage for the adum3151 / adum3152 / adum3153 isolators are detailed in tabl e 1 5 . insulation wear out the lifetime of insulation due to wear out is dete rmined by its thickness, the material properties, and the voltage stress applied. it is important to verify that the product lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the s ame as the working voltage supported for tracking. it is the working voltage applicable to tracking that is specified in most standards. testing and modeling have shown that the primary driver of long - term degradation is displacement current in the polyimi de insulation causing incremental damage. the stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because this reflects isolation from line voltage. h owever, many practical applications have combinations of 60 hz ac and dc across the barrier, as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in equation 2. for insulation wear out with the polyimide materials used in this product, the ac rms v oltage determines the product lifetime. 2 2 dc rms ac rms v v v + = dc rms rms ac v v v ? = v ac rms is the time varying portion of the working voltage. v dc is the dc offset of the working voltage. v rms is the total rms working voltage. calculation and use of parameters example the following is an example that frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms, and a 400 v dc bus voltage is present on the other sid e of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device, see figure 19 and the following equations. isol a tion vo lt age time v ac rms v rms v dc 12368-019 v peak figure 19 . critical voltage example the working voltage across the barrier from equation 1 is 2 2 dc rms ac rms v v v + = + = rms v v rms = 466 v this is the workin g voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. the ac rms voltage can be obt ained from equation 2. 2 2 dc rms rms ac v v v ? = ? = rms ac v v ac rms = 240 v rms in this case, the ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for the working voltage listed in table 19 for the expected lifetime, under a 60 hz sine wave, and it is well within the limit for a 50 - year service lif e. note that the dc working voltage limit in tabl e 19 is set by the creepage of the package as specified in iec 60664 - 1. this value may differ for specific system le vel standards . rev. a | page 21 of 22
adum3151/adum3152/adum3153 data sheet outline dimensions compliant t o jedec s t andards mo-150-ae 060106- a 20 1 1 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 20 . 20 - lead shrink small outline package [ssop] (rs - 20) dimensions shown in millimeters ordering guide model 1 no. of inputs, v dd1 side no. of inputs, v dd2 side maximum data rate (mhz) maximum propagation delay, 5 v (ns) isolation rating (v ac) temperature range package description package option adum3151arsz 5 2 1 25 3750 ?40c to +125c 20 - lead ssop rs - 20 adum3151arsz - rl7 5 2 1 25 3750 ?40c to +125c 20- lead ssop, 7 tape and reel rs -20 adum3151brsz 5 2 17 14 3750 ?40c to +125c 20- lead ssop rs -20 adum3151brsz - rl7 5 2 17 14 3750 ?40c to +125c 20- lead ssop, 7 tape and reel rs -20 eval - adum3151z evaluation board adum3152arsz 4 3 1 25 3750 ?40c to +125c 20- lead ssop rs -20 adum3152arsz - rl7 4 3 1 25 3750 ?40c to +125c 20 - lead ssop, 7 tape and reel rs - 20 adum3152brsz 4 3 17 14 3750 ?40c to +125c 20- lead ssop rs -20 adum3152brsz - rl7 4 3 17 14 3750 ?40c to +125c 20- lead ssop, 7 tape and reel rs -20 ADUM3153ARSZ 3 4 1 25 3750 ?40c to +125c 20- lead ssop rs -20 ADUM3153ARSZ - rl7 3 4 1 25 3750 ?40c to +125c 20- lead ssop, 7 tape and reel rs -20 adum3153brsz 3 4 17 14 3750 ?40c to +125c 20- lead ssop rs -20 adum3153brsz - rl7 3 4 17 14 3750 ?40c to +125c 20- lead ssop, 7 tape and reel rs -20 1 z = rohs compliant part. ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12368 - 0- 3/15(a) rev. a | page 22 of 22

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